Hardware is catching up to software. hw.dev tracks where that is happening, where it is still broken, and what builders should do about it.
Hardware isn't slow because of physics. It's slow because of coordination, validation, and tooling.
Those constraints are starting to break.
The bottleneck is shifting to decision-making. The teams that win will be the ones that compress the loop:
Short posts on meaningful developments. What happened, why it matters, what it enables, operator read.
Arm ships CSS for Mobile 2 with C2 Ultra CPU and Mali G2-Ultra NX GPU, moving the silicon design entry point from raw IP integration to validated compute subsystems -- a structural change in how chip teams build AI products.
Researchers establish the first proton irradiation baseline for an open-source RTL-accessible ML accelerator (Tensil on Zynq UltraScale+), demonstrating that closed-box commercial IP cannot support the same verifiable fault characterization workflow.
TreeFI uses regression trees to stratify DNN value distributions by fault-sensitivity, cutting required fault injection campaigns 44x on average and 72x at the high end -- published at ICCAD 2026.
A windowed storage roofline framework proves that on bandwidth-saturated edge boards, expert prefetch is not just unhelpful -- it is net-negative, and the only fix is fitting the model into the fast tier.
Long-form essays on the shifts reshaping hardware development. What is changing, why now, who benefits, what builders should do.
Sequential design (algorithm first, hardware second) has a quantified cost. Three papers this week put numbers on it.
Three proofs in three weeks close the end-to-end AI design case. The constraint has shifted upstream.
Opinionated, living reference maps of the modern hardware development stack. Layers. Incumbents. Insurgents. Named gaps.
First cut at the layered map of modern hardware development (from design through manufacture) with named incumbents, insurgents, and gaps. Updated as the ground moves.
The end-to-end stack a modern hardware team actually runs on: design, simulation, test, CI, manufacturing. Layered, opinionated, with named gaps.
Where AI is actually compressing hardware cycle time today, layer by layer: RTL, place-and-route, DV, PCB, DFM, test authoring, supply.
The stack that lets every test run in CI, not a lab bench: unit, integration, HIL, on-target, and compliance. Where the gaps are.
What validation looks like when specs, tests, coverage, and sign-off artifacts all live in Git. The tools, the formats, the missing layer.
The workflow from idea to shipped unit (requirements, CAD, BOM, MFG, field) and which layers have been code-ified vs which are still PDFs in SharePoint.
hw.dev is operator-led. Software-first view of hardware. Everything-as-code. Shift-left testing. Product realization.
Not a news site. Not an aggregator. An intelligence layer: Signal to read the week, Analysis to read the shift, Stack Maps to read the space.
Future tools may include BOM Intelligence, Test Intelligence, Validation Intelligence, Supply Chain Intelligence, and Product Realization Intelligence. Intelligence is the identity; the tools are the follow-through.